Logic optimization

Logic optimization

Logic optimization a part of logic synthesis, is the process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. Generally the circuit is constrained to minimum chip area meeting a prespecified delay.


With the advent of logic synthesis, one of the biggest challenges faced by the EDA Industry was to find the best netlist representation of the given design description. While two-level logic optimization had long existed in the form of the Quine–McCluskey algorithm, later followed by the Espresso heuristic logic minimizer, the rapidly improving chip densities, and the wide adoption of HDLs for circuit description, formalized the logic optimization domain as it exists today.

Today, logic optimization is divided into various categories based on two criteria:

Based on circuit representation
* Two-level logic optimization
* Multi-level logic optimization"'

Based on circuit characteristics
* Sequential logic optimization
* Combinational logic optimization

While two-level circuit representation of circuits strictly refers to the flattened view of the circuit in terms of sum-of-products (SOPs)- more applicable to PLA implementation of design—multi-level representation is a more generic view of the circuit in terms of arbitrarily connected SOPs, POSs (product-of-sum), factored form etc. Logic optimization algorithms generally work either on the structural (SOPs, factored form) or functional (BDDs,ADDs) representation of the circuit.

Two-level versus multi-level representations

If we have two functions "F"1 and "F"2:

: F_1 = AB + AC + AD,,

: F_2 = A'B + A'C + A'E.,

The above 2-level representation takes six product terms and 24 transistors in CMOS Rep.

A functionally equivalent representation in multilevel can be:

: "P" = "B" + "C".

: "F"1 = "AP" + "AD".

: "F"2 = "A'P" + "A'E".

While the number of levels here is 3, the total number of product terms and literals reduce because of the sharing of the term B + C.

Similarly, we distinguish between sequential and combinational circuits, whose behavior can be described in terms of finite-state machine(FSM) state tables/diagrams or by Boolean functions and relations respectively.

See also

*Logic minimization
*Logic synthesis
*Electronic design automation
*Binary decision diagram


*"Synthesis and Optimization of Digital Circuits", by Giovanni De Micheli, ISBN 0-07-016333-2.

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