SSE4

SSE4 is an instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006 at the Fall 2006 Intel Developer Forum, with vague details in a white paper; [ [http://www.intel.com/technology/architecture-silicon/sse4-instructions/index.htm Intel Streaming SIMD Extensions 4 (SSE4) Instruction Set Innovation] , Intel.] more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation. [ [https://intel.wingateweb.com/published/BMAS005/BMAS005_100Eng.pdf Tuning for Intel SSE4 for the 45nm Next Generation Intel Core Microarchitecture] , Intel.] The [http://softwarecommunity.intel.com/isn/Downloads/Intel%20SSE4%20Programming%20Reference.pdf SSE4 Programming Reference] is available from Intel.

E4 subsets

Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as SSE4.1 in some Intel documentation, is available in Penryn. Additionally, SSE4.2, a second subset consisting of the 7 remaining instructions, will first be available in Core i7 (formerly Nehalem). Intel, unusually, credits feedback from developers as playing an important role in the development of the instruction set.

AMD also added two new SSE instructions that it named SSE4a. These instructions are not found in Intel's processors supporting SSE4.1 and alternatively AMD processors are not supporting Intel's SSE4.1. Support was added for SSE4a for unaligned SSE load-operation instructions (which formerly required 16-byte alignment). [cite news |last=Case |first=Loyd |title=AMD Unveils Barcelona Quad-Core Details |url=http://www.extremetech.com/article2/0,1697,2027634,00.asp |publisher=Ziff Davis |accessdate=2008-04-13]

Name confusion

It should be noted that what is now known as SSSE3 (Supplemental Streaming SIMD Extension 3), introduced in the Intel Core 2 processor line, was mistakenly referred to as SSE4 by the media during its development.

New instructions

Unlike all previous iterations of SSE, SSE4 contains instructions that execute operations which are not specific to multimedia applications. It features a number of instructions whose action is determined by a constant field, and, in a rather surprising move, a set of instructions which take XMM0 as an implicit third operand. In addition, SSE4 totally lacks support for operations on 64-bit MMX registers; SIMD integer operations can be carried out on 128-bit XMM registers only.

Several of these instructions are enabled by the single-cycle shuffle engine in Penryn.

E4.1

ee also

*SSE
*SSE2
*SSE3
*SSSE3
*SSE5
*AVX
*SIMD
*3DNow! Professional
*Intel Core 2
*Tejas and Jayhawk
*x86 instruction listings

References