VerilogCSP

VerilogCSP

In integrated circuit design, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack.

External links

* [http://jungfrau.usc.edu/new/research/current/verilogcsp/index.html VerilogCSP Homepage]


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  • Verilogcsp — In integrated circuit design, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits.… …   Wikipedia

  • Communicating sequential processes — In computer science, Communicating Sequential Processes (CSP) is a formal language for describing patterns of interaction in concurrent systems.[1] It is a member of the family of mathematical theories of concurrency known as process algebras, or …   Wikipedia

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