Technology CAD

Technology CAD

Technology CAD (or Technology Computer Aided Design, or TCAD) is a branch of electronic design automation that models semiconductor fabrication and semiconductor device operation. The modeling of the fabrication is termed Process TCAD, while the modeling of the device operation is termed Device TCAD. Included are the modelling of process steps (such as diffusion and ion implantation), and modelling of the behavior of the electrical devices based on fundamental physics, such as the doping profiles of the devices. TCAD may also include the creation of "compact models" (such as the well known SPICE transistor models), which try to capture the electrical behavior of such devices but do not generally derive them from the underlying physics. (However, the SPICE simulator itself is usually considered as part of ECAD rather than TCAD.)

400px|right|thumb|Hierarchy of technology CAD tools building from theprocess level to circuits. Left side icons show typical manufacturingissues; right side icons reflect MOS scaling results based on TCAD(CRC Electronic Design Automation for IC Handbook, Chapter 25)

From the diagram on the right:
* See SPICE for an example of a circuit simulator
* See semiconductor device modeling for a description of modeling devices from dopant profiles.
* See semiconductor process simulation for the generation of these profiles


Technology files and design rules are essential building blocks of the integrated circuit design process. Their accuracy and robustness over process technology, its variability and the operating conditions of the IC--environmental, parasitic interactions and testing, including adverse conditions such as electro-static discharge--are critical in determining performance, yield and reliability. Development of these technology and design rule files involves an iterative process that crosses boundaries of technology and device development, product design and quality assurance. Modeling and simulation play a critical role in support of many aspects of this evolution process.

The goals of TCAD start from the physical description of integrated circuit devices, considering both the physical configuration and related device properties, and build the links between the broad range of physics and electrical behavior models that support circuit design. Physics-based modeling of devices, in distributed and lumped forms, is an essential part of the IC process development. It seeks to quantify the underlying understanding of the technology and abstract that knowledge to the device design level, including extraction of the key parameters that support circuit design and statistical metrology. Although the emphasis here is on Metal Oxide Semiconductor (MOS) transistors--the workhorse of the IC industry--it is useful to briefly overview the development history of the modeling tools and methodology that has set the stage for the present state-of-the-art.


The evolution of technology computer-aided design (TCAD)--the synergistic combination of process, device and circuit simulation and modeling tools—finds its roots in bipolar technology, starting in the late 1960s, and the challenges of junction isolated, double-and triple-diffused transistors. These devices and technology were the basis of the first integrated circuits; nonetheless, many of the scaling issues and underlying physical effects are integral to IC design, even after four decades of IC development. With these early generations of IC, process variability and parametric yield were an issue—a theme that will reemerge as a controlling factor in future IC technology as well.

Process control issues--both for the intrinsic devices and all the associated parasitics--presented formidable challenges and mandated the development of a range of advanced physical models for process and device simulation. Starting in the late 1960s and into the 1970s, the modeling approaches exploited were dominantly one- and two-dimensional simulators. While TCAD in these early generations showed exciting promise in addressing the physics-oriented challenges of bipolar technology, the superior scalability and power consumption of MOS technology revolutionized the IC industry. By the mid-1980s, CMOS became the dominant driver for integrated electronics. Nonetheless, these early TCAD developments (cite 1 and 2) set the stage for their growth and broad deployment as an essential toolset that has leveraged technology development through the VLSI and ULSI eras which are now the mainstream.

IC development for more than a quarter-century has been dominated by the MOS technology. In the 1970s and 1980s NMOS was favored owing to speed and area advantages, coupled with technology limitations and concerns related to isolation, parasitic effects and process complexity. During that era of NMOS-dominated LSI and the emergence of VLSI, the fundamental scaling laws of MOS technology were codified and broadly applied (cite 3). It was also during this period that TCAD reached maturity in terms of realizing robust process modeling (primarily one-dimensional) which then became an integral technology design tool, used universally across the industry (cite 4). At the same time device simulation, dominantly two-dimensional owing to the nature of MOS devices, became the work-horse of technologists in the design and scaling of devices (cite 5 and 6). The transition from NMOS to CMOS technology resulted in the necessity of tightly-coupled and fully-2D simulators for process and device simulations. This third generation of TCAD tools became critical to address the full complexity of twin-well CMOS technology (see Figure 3a), including issues of design rules and parasitic effects such as latchup (cite 7 and 8). An abbreviated but prospective view of this period, through the mid-1980s, is given in (cite 9); and from the point of view of how TCAD tools were used in the design process, see (cite 10).

Modern TCAD

Today the requirements for and use of TCAD cross-cut a very broad landscape of design automation issues, including many fundamental physical limits. At the core are still a host of process and device modeling challenges that support intrinsic device scaling and parasitic extraction. These applications include technology and design rule development, extraction of compact models and more generally design for manufacturability (DFM) (cite 11). The dominance of interconnects for giga-scale integration (transistor counts in O(billion)) and clocking frequencies in O (10 gigahertz)) have mandated the development of tools and methodologies that embrace patterning by electro-magnetic simulations—both for optical patterns and electronic and optical interconnect performance modeling—as well as circuit-level modeling. This broad range of issues at the device and interconnect levels, including links to underlying patterning and processing technologies, is summarized in Figure 1 and provides a conceptual framework for the discussion that now follows.

400px|right|thumb|Figure 1: Hierarchy of technology CAD tools building from theprocess level to circuits. Left side icons show typical manufacturingissues; right side icons reflect MOS scaling results based on TCAD(CRC Electronic Design Automation for IC Handbook, Chapter 25)Figure 1 depicts a hierarchy of process, device and circuit levels of simulation tools. On each side of the boxes indicating modeling level are icons that schematically depict representative applications for TCAD. The left side gives emphasis to Design For Manufacturing (DFM) issues such as: shallow-trench isolation (STI), extra features required for phase-shift masking (PSM) and challenges for multi-level interconnects that include processing issues of chemical-mechanical planarization (CMP), and the need to consider electro-magnetic effects using electromagnetic field solvers. The right side icons show the more traditional hierarchy of expected TCAD results and applications: complete process simulations of the intrinsic devices, predictions of drive current scaling and extraction of technology files for the complete set of devices and parasitics.

Figure 2 again looks at TCAD capabilities but this time more in the context of design flow information and how this relates to the physical layers and modeling of the electronic design automation (EDA) world. Here the simulation levels of process and device modeling are considered as integral capabilities (within TCAD) that together provide the "mapping" from mask-level information to the functional capabilities needed at the EDA level such as compact models ("technology files") and even higher-level behavioral models. Also shown is the extraction and electrical rule checking (ERC); this indicates that many of the details that to date have been embedded in analytical formulations, may in fact also be linked to the deeper TCAD level in order to support the growing complexity of technology scaling.


*"Electronic Design Automation For Integrated Circuits Handbook", by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field of electronic design automation. This summary was derived (with permission) from Vol II, Chapter 25, "Device Modeling—from physics to electrical parameter extraction", by Robert W. Dutton,Chang-Hoon Choi and Edwin C. Kan.

See also

(1) H.J. DeMan and R. Mertens, [ SITCAP--A simulator of bipolar transistors for computer-aided circuit analysis programs] , International Solid-State Circuits Conference (ISSCC), Technical Digest, pp. 104-5, February, 1973

(2) R.W. Dutton and D.A. Antoniadis, [ Process simulation for device design and control] , International Solid-State Circuits Conference (ISSCC), Technical Digest, pp. 244-245, February, 1979

(3) R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rodeout, E. Bassous and A.R. LeBlanc, [ Design of ion-implanted MOSFETs with very small physical dimensions] , IEEE Jour. Solid-State Circuits, vol. SC-9, pp.256-268, October, 1974.

(4) R.W. Dutton and S.E. Hansen, [ Process modeling of integrated circuit device technology] , Proceeding IEEE, vol. 69, no. 10, pp. 1305-1320, October, 1981.

(5) P.E. Cottrell and E.M. Buturla, "Two-dimensional static and transientsimulation of mobile carrier transport in a semiconductor," Proceedings NASECODE I(Numerical Analysis of Semiconductor Devices), pp. 31-64, Boole Press, 1979.

(6) S. Selberherr, W. Fichtner, and H.W. Potzl, "Minimos--a program package tofacilitate MOS device design and analysis," Proceedings NASECODE I (NumericalAnalysis of Semiconductor Devices), pp. 275-79, Boole Press, 1979.

(7) C.S. Rafferty, M.R. Pinto, and R.W. Dutton, [ Iterative methods in semiconductor device simulation] , IEEE Trans. Elec. Dev., vol. ED-32, no.10, pp.2018-2027, October, 1985.

(8) M.R. Pinto and R.W. Dutton, [ Accurate trigger condition analysis for CMOS latchup] , IEEE Electron Device Letters, vol. EDL-6, no. 2, February, 1985.

(9) R.W. Dutton, [ Modeling and simulation for VLSI] , International Electron Devices Meeting (IEDM), Technical Digest, pp. 2-7, December, 1986.

(10) K.M. Cham, S.-Y. Oh, D. Chin and J.L. Moll, Computer-Aided Design and VLSIDevice Development, Kluwer Academic Publishers (KAP), 1986. ISBN 9780898382044

(11) R.W. Dutton and A.J. Strojwas, doi-inline|10.1109/43.898831|Perspectives on technology and technology-driven CAD, IEEE Trans. CAD-ICAS, vol. 19, no. 12, pp. 1544-1560, December, 2000.

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