Placement (EDA)

Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area. An inferior placement assignment will not only affect the
chip's performance but might also make it nonmanufacturable by producing excessive wirelength, whichis beyond available routing resources. Consequently, a placer must perform the assignment while optimizinga number of objectives to ensure that a circuit meets its performance demands. Typical placementobjectives include
*Total wirelength: Minimizing the total wirelength, or the sum of the length of all the wires in the design, is the primary objective of most existing placers. This not only helps minimize chip size, and hence cost, but also minimizes power and delay, which are proportional to the wirelength and wirelength squared, respectively.
*Timing: The clock cycle of a chip is determined by the delay of its longest path, usually referred to as the critical path. Given a performance specification, a placer must ensure that no path exists with delay exceeding the maximum specified delay.
*Congestion: While it is necessary to minimize the total wirelength to meet the total routing resources, it is also necessary to meet the routing resources within various local regions of the chip’s core area. A congested region might lead to excessive routing detours, or make it impossible to complete all routes.
*Power: Power minimization typically involves distributing the locations of cell components so as to reduce the overall power consumption, alleviate hot spots, and smooth temperature gradients.
*A secondary objective is placement runtime minimization.

Placement within the EDA design flow

A placer takes a given synthesizedcircuit netlist together with a technology library and produces a valid placement layout. The layoutis optimized according to the aforementioned objectives and ready for cell resizing and buffering — a stepessential for timing and signal integrity satisfaction.
Clock-tree synthesis and routing follow, completing the physical design process. In many cases, parts of, or the entire, physical design flow are iterated a numberof times until design closure is achieved.

In the case of application-specific integrated circuits, or ASICs, the chip’s core layout area comprises anumber of fixed height rows, with either some or no space between them. Each row consists of a numberof sites which can be occupied by the circuit components. A free site is a site that is not occupied by any component. Circuit components are either standard cells, macro blocks, or I/O pads. Standard cells have afixed height equal to a row’s height, but have variable widths. The width of a cell is an integral number ofsites. On the other hand, blocks are typically larger than cells and have variable heights that can stretch amultiple number of rows. Some blocks can have preassignedlocations — say from a previous floorplanning process — which limit the placer’s task to assigning locationsfor just the cells. In this case, the blocks are typically referred to by fixed blocks. Alternatively, some orall of the blocks may not have preassigned locations. In this case, they have to be placed with the cells inwhat is commonly referred to as mixed-mode placement.

In addition to ASICs, placement retains its prime importance in gate array structures such as field-programmable gate arrays (FPGAs). In FPGAs, placement maps the circuit’s subcircuits into programmable FPGA logic blocks in a manner that guarantees the completion of the subsequent stage of routing.

Basic techniques

*Analytical techniques approximate the wirelength objective using quadratic [cite journal
title=GORDIAN: VLSI placement by quadratic programming and slicing optimization |doi= 10.1109/43.67789
author= Kleinhans, J.M.; Sigl, G.; Johannes, F.M.; Antreich, K.J.;
journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
volume=10 |issue=3 |month=March |year=1991 |pages= 356–365 ] or nonlinear [cite journal
doi=10.1109/TCAD.2005.846366
title=Implementation and extensibility of an analytic placer
author= Kahng, A.B.; Qinke Wang;
journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
volume=24| issue=5| month= May |year=2005| pages=734–747 ] formulations.
*The advent of min-cut partitioners paved the way to the introduction of min-cut placers [cite conference
title=doi-inline|10.1109/DAC.2000.855358|Can recursive bisection alone produce routable placements?
author=Caldwell, A.E.; Kahng, A.B.; Markov, I.L.;
booktitle=Proceedings of the 37th Design Automation Conference
month=June| year=2000 |pages=477 - 482 ] .
*Another thread of placement techniques [cite journal
url=http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=1052337
title=The TimberWolf placement and routing package] ,
author=Sechen, C. and Sangiovanni-Vincentelli, A.
journal=Solid-State Circuits, IEEE Journal of
volume=20,
number=2,
pages=510--522
year=1985
doi=10.1109/JSSC.1985.1052337 ] started with the proposal of simulated annealing as a general combinatorial optimization technique [cite journal
title=Optimization by Simulated Annealing
author=Kirkpatrick, S. and Gelatt Jr, CD and Vecchi, MP,
journal=Science,
volume=220,
number=4598,
pages=671,
year=1983
doi=10.1126/science.220.4598.671
pmid=17813860 ] .

See also

*Electronic design automation
*Design flow (EDA)
*Integrated circuit design

Further reading/External links

The following academic journals provide further information on EDA
* IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems
* ACM Transactions On Design Automation

References

*"Electronic Design Automation For Integrated Circuits Handbook", by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field of Electronic Design Automation. The above summary was derived, with permission, from Volume II, Chapter 5, "Digital Layout -- Placement" by Andrew Kahng and Sherief Reda.