Small-outline integrated circuit

Small-outline integrated circuit

A small-outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30 - 50% less than an equivalent DIP, with a typical thickness that is 70% less. They are generally available in the same pinouts as their counterpart DIP ICs. The convention for naming the package is 'SOIC' or sometimes just 'SO' followed by the number of pins. For example, a 14-pin 4011 would be housed in an SOIC-14 or SO-14 package.

Small-outline J-leaded package (SOJ) is a version of SOIC with J-type leads instead of gulf-wing leads. [http://www.siliconfareast.com/packages.htm]

JEDEC and EIAJ standards

'SOIC' actually refers to at least two different package standards. The EIAJ SOIC body is approximately 5.3mm (0.209") wide while the JEDEC SOIC body is approximately 3.8mm (0.150") wide. The EIAJ packages are also thicker and slightly longer. Otherwise the packages are similar.

Note that because of this, SOIC is not specific enough of a term to describe parts which are interchangeable. Many electronic retailers will list parts in either package as "SOIC" whether they are referring to the JEDEC or EIAJ standards. The wider EIAJ packages are more common with higher pin count ICs, but there is no guarantee that an SOIC package with any number of pins will be either one or the other.

General package characteristics

This package is shorter and narrower than DIPs, the side-to-side pitch being 6 mm for an SOIC-14 (from lead tip to lead tip) and the body width being 3.9 mm. These dimensions differ depending on the SOIC in question, and there are several variants. This package has "gull wing" leads protruding from the two long sides and a lead spacing of 0.050 inches.

The picture below shows the general shape of an SOIC, with major dimensions. The values of these dimensions (in mm) for common SOICs is shown in the table.

C Clearance between IC body and PCB H Total Carrier Height T Lead Thickness L Total Carrier Length LW Lead Width LL Lead Length P Pitch WB IC Body Width WL Lead-to-Lead Width O End Overhang

OP

After SOIC came a family of smaller form factors, Small Outline Package (SOP), with a pin spacing of 0.65 mm:
*Plastic Small-Outline Package (PSOP)
*Thin Small-Outline Package (TSOP)
*Shrink Small-Outline Package (SSOP)
*Thin-Shrink Small Outline Package (TSSOP)

The ICs on DRAM memory modules were usually TSOPs until they were replaced by ball grid array (BGA).

External links

* [http://focus.ti.com/lit/ml/msoi002e/msoi002e.pdf Texas Instruments CAD drawing of SOIC-8]
* [http://www.fairchildsemi.com/dwg/M0/M08A.pdf Fairchild CAD drawing and footprint for SOIC-8]
* [http://www.atmel.com/dyn/products/packagecard.asp?family_id=647&part_id=2483&package_id=293&green=1 Dimensions for EIAJ SOIC-8]
* [http://www.atmel.com/dyn/products/packagecard.asp?family_id=616&part_id=4333&package_id=292&green=1 Dimensions for JEDEC SOIC-8]


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