Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Resistance, capacitance and inductance of wires in a chip are known as parasitic data. SPEF is used for delay calculation and ensuring signal integrity of a chip which eventually determines its speed of operation.
SPEF is most popular specification for parasitic exchange between different tools of EDA domain during any phase of design.
The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System.
SPEF syntax is roughly:And repeat (include *END) for other nets.
In order to reduce file size, aliasing is possible, using a name-
These symbols (including the *) can then be substituted for the longer words anywhere.
Note: SPEF is not the same as SPF (including DSPF and RSPF). Detailed Standard Parasitic Format is a very different format, meant to be useful in a Spice simulation. For example, NET sections do not have endings, and comments should start with two asterisks.A brief syntax of the DSPF format is as shown:
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