High-k dielectric

High-k dielectric

The term high-κ dielectric refers to a material with a high dielectric constant (κ) (as compared to silicon dioxide) used in semiconductor manufacturing processes which replaces the silicon dioxide gate dielectric. The implementation of high-κ gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components, colloquially referred to as extending Moore's Law.

Need for high-κ materials

Silicon dioxide has been used as a gate oxide material for decades. As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current and device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to unwieldy power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-κ material allows increased gate capacitance without the concomitant leakage effects.

First principles

The gate oxide in a MOSFET can be modeled as a parallel plate capacitor. Ignoring quantum mechanical and depletion effects from the Si substrate and gate, the capacitance "C" of this parallel plate capacitor is given by: C=frac{kappavarepsilon_{0}A}{t}


* , A is the capacitor area
* , kappa is the relative dielectric constant of the material (3.9 for silicon dioxide)
* , varepsilon_{0} is the permittivity of free space
* , t is the thickness of the capacitor oxide insulator

Since leakage limitation constrains further reduction of , t, an alternative method to increase gate capacitance is alter , kappa by replacing silicon dioxide with a high-, kappa material. In such a scenario, a thicker gate layer might be used which can reduce the leakage current flowing through the structure as well as improving the gate dielectric reliability.

Gate capacitance impact on drive current

The drive current , I_D for a MOSFET can be written (using the gradual channel approximation) as I_{D,Sat} = frac{W}{L} mu, C_{inv}frac{(V_{G}-V_{th})^2}{2}

* W is the width of the transistor channel
* L is the channel length
* mu is the channel carrier mobility (assumed constant here)
* C_{inv} is the capacitance density associated with the gate dielectric when the underlying channel is in the inverted state
* V_{G} is the voltage applied to the transistor gate
* V_{D} is the voltage applied to the transistor drain
* V_{th} is the threshold voltage

The term (V_{G}-V_{th}) is limited in range due to reliability and room temperature operation constraints, since too large a V_{G} would create an undesirable, high electric field across the oxide. Furthermore, V_{th} cannot easily be reduced below about 200 mV, because leakage currents due to increased oxide leakage (that is, assuming high-κ dielectrics are not available) and subthreshold conduction raise stand-by power consumption to unacceptable levels. (See the industry roadmap [cite web | url = http://www.itrs.net/Links/2006Update/FinalToPost/04_PIDS2006Update.pdf | work = International Technology Roadmap for Semiconductors: 2006 Update | title = Process Integration, Devices, and Structures] , which limits threshold to 200 mV, and Roy "et al." cite book
author=Kaushik Roy, Kiat Seng Yeo
title=Low Voltage, Low Power VLSI Subsystems
year= 2004
page=Fig. 2.1, p. 44
publisher=McGraw-Hill Professional
] ). Thus, according to this simplified list of factors, an increased I_{D,sat} requires a reduction in the channel length or an increase in the gate dielectric capacitance.

Materials and considerations

Replacing the silicon dioxide gate dielectric with another material adds complexity to the manufacturing process. Silicon dioxide can be formed by oxidizing the underlying silicon, ensuring a uniform, conformal oxide and high interface quality. As a consequence, development efforts have focused on finding a material with a requisitely high dielectric constant that can be easily integrated into a manufacturing process. Other key considerations include band alignment to silicon (which may alter leakage current), film morphology, thermal stability, maintenance of a high mobility of charge carriers in the channel and minimization of electrical defects in the film/interface. Materials which have received considerable attention are hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide, typically deposited using atomic layer deposition.

It is expected that defect states in the high-k dielectric can influence its electrical properties. Defect states can be measured for example by using zero-bias thermally stimulated current, zero-temperature-gradient zero-bias thermally stimulated current spectroscopy [ [http://dx.doi.org/10.1063/1.119590 Cookies Required ] ] [ [http://dx.doi.org/10.1063/1.2199590 Cookies Required ] ] , or Inelastic electron tunneling spectroscopy (IETS).

Use in industry

The industry has employed oxynitride gate dielectrics since the 1990s, wherein a conventionally formed silicon oxide dielectric is infused with a small amount of nitrogen. The nitride content subtly raises the dielectric constant and is thought to offer other advantages, such as resistance against dopant diffusion through the gate dielectric.

In early 2007, Intel announced the deployment of hafnium-based high-k dielectrics in conjunction with a metallic gate for components built on 45 nanometer technologies, and has shipped it in the 2007 processor series codenamed Penryn. [ [http://www.intel.com/technology/silicon/45nm_technology.htm Intel 45nm High-k Silicon Technology Page] ] [ [http://www.spectrum.ieee.org/oct07/5553 IEEE Spectrum: The High-k Solution] ] At the same time, IBM announced plans to transition to high-k materials, also hafnium-based, for some products in 2008. While not identified, it is most likely the dielectrics used by these companies are some form of nitrided hafnium silicates (HfSiON). HfO2 and HfSiO are susceptible to crystallization during dopant activation annealing. NEC Electronics has also announced the use of a HfSiON dielectric in their 55 nm "UltimateLowPower" technology. [ [http://www.necel.com/process/en/lowpower_overview.html UltimateLowPower Technology | Advanced Process Technology | Technology | NEC Electronics ] ] However, even HfSiON is susceptible to trap-related leakage currents, which tend to increase with stress over device lifetime. The higher the hafnium concentration, the more severe the issue. However, there is no absolute guarantee that hafnium will be the basis of future high-k dielectrics. The 2006 ITRS roadmap predicts the implementation of high-k materials to be commonplace in the industry by 2010.


Further reading

* [http://dx.doi.org/10.1063/1.1361065 Review article] by Wilk "et al" in the Journal of Applied Physics
* Houssa, M. (Ed.) (2003) "High-k Dielectrics" Institute of Physics ISBN 0-7503-0906-7 [ [http://www.crcpress.com/shopping_cart/products/product_detail.asp?sku=IP365 CRC Press Online ] ]
* Huff, H.R., Gilmer, D.C. (Ed.) (2005) "High Dielectric Constant Materials : VLSI MOSFET applications" Springer ISBN 3-540-21081-4
* Demkov, A.A, Navrotsky, A., (Ed.) (2005) "Materials Fundamentals of Gate Dielectrics" Springer ISBN 1-4020-3077-0
* "High dielectric constant gate oxides for metal oxide Si transistors" Robertson, J. ("Rep. Prog. Phys." 69 327-396 2006) "Institute Physics Publishing" [ [http://dx.doi.org/10.1088/0034-4885/69/2/R02 High dielectric constant gate oxides ] ]
* Media coverage of March, 2007 Intel/IBM announcements [ [http://news.bbc.co.uk/1/hi/technology/6299147.stm BBC NEWS | Technology | Chips push through nano-barrier ] ] [ [http://www.nytimes.com/2007/01/27/technology/27chip.html NY Times Article (1/27/07)] ]
* Gusev, E. P. (Ed.) (2006) "Defects in High-k Gate Dielectric Stacks: Nano-Electronic Semiconductor Devices", Springer ISBN 1-402-04366X

See also

* Low-k
* Silicon germanium
* Silicon on insulator
* Hafnium on Insulator
* Zirconium on Insulator

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