Die shrink

Semiconductor manufacturing processes
10 µm — 1971 3 µm — 1975 1.5 µm — 1982 1 µm — 1985 800 nm (.80 µm) — 1989 600 nm (.60 µm) — 1994 350 nm (.35 µm) — 1995 250 nm (.25 µm) — 1998 180 nm (.18 µm) — 1999 130 nm (.13 µm) — 2000 90 nm — 2002 65 nm — 2006 45 nm — 2008 32 nm — 2010 22 nm — 2011 16 nm — approx. 2013 11 nm — approx. 2015
Half-nodes

The term "die shrink" (sometimes "optical shrink" or "process shrink") refers to a simple semiconductor scaling of semiconductor devices, mainly transistors. The act of shrinking a die is to create a somewhat identical circuitry using a more advanced fabrication process, usually involving an advance of lithographic node. This reduces overall costs of a chip company, as the absence of major architectural changes to the processor lowers research and development costs, while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in greater revenue per product sold.

Details

"Die shrink" is popular among semiconductor companies, such as Intel, AMD (including the former ATI) and NVIDIA for enriching their product lines. Examples in the 2000s include the codenamed Cedar Mill Pentium 4 processors (from 90 nm CMOS to 65 nm CMOS) and Penryn Core 2 processors (from 65 nm CMOS to 45 nm CMOS), the codenamed Brisbane Athlon 64 X2 processors (from 90 nm SOI to 65 nm SOI), and various generations of GPUs from both ATI and NVIDIA. In January 2010, Intel released Clarkdale Core i5 and Core i7 processors fabricated with a 32 nm process, down from a previous 45 nm process used in older iterations of the Nehalem processor microarchitecture.

Die shrink is beneficial to end-users as shrinking a die reduces the current leakage in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices.

Half-shrink

In CPU fabrications, it is noted that a "die shrink" always involves an advance to a lithographic node as defined by ITRS (for example, 600 nm, 350 nm, 250 nm, 180 nm, 130 nm, 90 nm to 65 nm then 45 nm nodes and so on). For GPU and SoC manufacturing, the "die shrink" usually first involves shrinking the die on a node not defined by the ITRS, for instance the 150 nm, 110 nm, 80 nm, 55 nm and more currently 40 nm nodes (expected subsequent half-nodes are 28 nm and 20 nm), sometimes referred to as "half-node". This is a stopgap between two ITRS defined lithographic nodes (thus called a "half-node shrink") before further shrink to the lower ITRS defined nodes occurs, which helps save further R&D cost.

Half-shrink

Main ITRS node	Stopgap half-node
180 nm	150nm
130nm	110nm
90nm	80nm
65nm	55nm
45nm	40nm
32nm	28nm
22nm	20nm
16nm	14nm
11nm	10nm

See also

Electronics portal

• Integrated circuit
• Semiconductor device fabrication
• Lithography

External links

• 0.11 µm Standard Cell ASIC
• EETimes: ON Semi offers 110-nm ASIC platform
• Renesas 55 nm process features
• RDA, SMIC make 55-nm mixed-signal IC
• Globalfoundries 40nm
• UMC 45/40nm
• SiliconBlue tips FPGA move to 40-nm
• Globalfoundries 28nm, Leading-Edge Technologies
• TSMC Reiterates 28 nm Readiness by Q4 2011
• Design starts triple for TSMC at 28-nm