Warp (Cypress)

Warp is a VHDL low cost development system for CPLD by Cypress Semiconductor Corporation. The cost is low (about $99) because of its simple architecture. Warp contains an interactive simulator (Aldec) and a compiler (Galaxy).

Unlike the IEEE 1164 standard, Warp supports only 6 logic levels: "0", "1", "Z", "L", "H" and "-"; "X" (strong drive logic unknown) and "W" (Weak drive unknown) aren't supported. The arithmetic operators can be supported by system only if the appropriate library is linked.

With Warp a project can be written only with VHDL both with behavioral and structural architecture. Aldec is the simulator that can do pre-synthesis and post-synthesis simulation. Pre-synthesis simulation is useful to verify that VHDL program works as expected and post-synthesis simulation keeps also propagation delay.

Projecting steps

* VHDL or Verilog code writing with graphic editor
* Code simulation to verify that program works as expected
* Synthesis after choosing a specific device
* Automatic fitting (mapping logic functions into PLD logic blocks)
* Post synthesis simulation with timing informations

At the end of the process ISR, a programming software, generates a "jam" file containing the bit streams needed to programming PLD macrocells.

External links

* Cypress Semiconductor