NISC

This page describes methods and tools that support no-instruction-set-computer (NISC) technology. NISC is a new architecture and compiler technology for designing custom processors and hardware accelerators.

Overview

NISC is a Statically-Scheduled Horizontal Nanocoded Architecture (SSHNA). The term "statically scheduled" means that the operation scheduling and hazard handling are done by a compiler. The term "horizontal nanocoded" means that NISC does not have any predefined instruction set or microcode. The compiler generates nanocodes which directly control functional units, registers and multiplexers of a given datapath. Giving low-level control to compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology can be summarized as follows:
(1) Simpler controller: no hardware scheduler, no instruction decoder
(2) Better performance: more flexible architecture, better resource utilization
(2) Easier to design: no need for designing instruction-sets

Instruction-set and controller of processors are the most tedious and time-consuming parts to design. By eliminating these two, design of custom processing elements become significantly easier.

Furthermore, the datapath of NISC processors can be even generated automatically for a given application. Therefore, designers productivity is improved significantly.
Since NISC datapaths are very efficient and can be generated automatically, NISC technology is comparable to high level synthesis (HLS) or "c to HDL" synthesis approaches. In fact, one of the benefits of this architecture style is its capability to bridge these two technologies (custom processor design and HLS).

History

In the past, microprocessor design technology evolved from Complex Instruction Set Computer (CISC) to Reduced Instruction Set Computer (RISC). In the early days of the computer industry, compiler technology did not exist and programming was done in assembly. To make programming easier, computer architects created complex instructions, which were direct representations of high level functions of high level programming languages. Another force that encouraged instruction complexity was the lack of large memory blocks.As compiler and memory technologies advanced, RISC architectures were introduced. RISC architectures need more instruction memory and require a compiler to translate high-level languages to RISC assembly code. Further advancement of compiler and memory technologies leads to emerging Very Long Instruction Word (VLIW) processors, where compiler controls the schedule of instructions and handles data hazards. NISC is a successor of VLIW processors. In NISC, compiler has both horizontal and vertical control of the operations in the datapath. Therefore, the hardware is much simpler. However the control memory size is larger than the previous generations. To address this issue, low-overhead compression techniques can be used.

NISC technology tools

[http://www.cecs.uci.edu/~nisc NISC Toolset (a C-to-Verilog and custom processor design tool) in CECS UC, Irvine]

References

Read more about NISC in Chapter 2 of the following book: