Value change dump

Value change dump is an ASCII-based format for dumpfiles generated by EDA logic simulation tools. The standard, four-value VCD format was defined along with the Verilog hardware description language by the IEEE Standard 1364-1995 in 1995. An Extended VCD format defined six years later in the IEEE Standard 1364-2001 supports the logging of signal strength and directionality. The simple and yet compact structure of the VCD format has allowed its use to become ubiquitous and to spread into non-Verilog tools such as the VHDL simulator GHDL and various kernel tracers.

Structure

The VCD file comprises a header section with date, simulator, and timescale information; a variable definition section; and a value change section, in that order. The sections are not explicitly delineated within the file, but are identified by the inclusion of keywords belonging to each respective section.

Header section

The header section of the VCD file includes a timestamp, a simulator version number, and a timescale, which maps the time increments listed in the value change section to simulation time units.

Variable definition section

The variable definition section of the VCD file contains scope information as well as lists of signals instantiated in a given scope. Each variable is assigned an arbitrary, compact ASCII identifier for use in the value change section. The scope type definitions closely follow Verilog concepts, and include the types "module", "task", "function", and "fork".

Value change section

The value change section contains a series of time-ordered value changes for the signals in a given simulation model.

Syntax

VCD keywords are marked by a leading $. In general every keyword starts a section which is terminated by an $end keyword.

Example:

$timescale 1 ns $end

Another example of a file is: $timescale 1ps $end $scope module logic $end $var wire 8 # data $end $var wire 1 $ data_valid $end $var wire 1 % en $end $var wire 1 & rx_en $end $var wire 1 ' tx_en $end $var wire 1 ( empty $end $var wire 1 ) underrun $end $upscope $end $enddefinitions $end #0 b10000001 # 0$ 1% 0& 1' 0( 0) #2211 0' #2296 b0 # 1$ #2302 0$ #2303

The code above defines 7 signals by using $var:

$var type bitwidth id name

The id is used later on the wave description, the wave description starts after $enddefinitions $end, and is base on timestamps, starting with #. On each timestamp specified the list of signals that their value were modified. This is done by the pair:

new_value id

notice a white space is not separating between them.

All VCD tokens are delineated by whitespace.

ee also

*Waveform viewer

External links

* [http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=20656&isYear=2001 IEEE Std 1364-2001] – The official standard for Verilog 2001 (not free).