Reference Verification Methodology
- Reference Verification Methodology
The Reference Verification Methodology (RVM) is a complete set of metrics and methods for performing Functional verification of complex designs such as for Application-specific integrated circuits or other semiconductor devices. It was published by Synopsys in 2003.
The SystemVerilog implementation of the RVM is known as the VMM (Verification Methodology Manual). It contains a small library of base classes.
External links
* [http://www.vmm-sv.org Verification Methodology Manual] for SystemVerilog
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