Overlay Control

Silicon wafers are currently manufactured in a sequence of steps, each stage placing a pattern of material on the wafer; in this way transistors, contacts, etc., all made of different materials, are laid down. In order for the final device to function correctly, these separate patterns must be aligned correctly - for example contacts, lines and transistors must all line up.

Overlay control is the term used to define the control of this pattern-to-pattern alignment. It has always played an important role in semiconductor manufacturing, helping to monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind can cause short circuits and connection failures, which in turn impact fab yield and profit margins.

Overlay control has become even more critical now because the combination of increasing pattern density and innovative techniques such as double patterning and 193 nm immersion lithography creates a novel set of pattern-based yield challenges at the 45 nm technology node and below. This combination causes error budgets to shrink below 30 percent of design rules, where existing overlay metrology solutions cannot meet total measurement uncertainty (TMU) requirements.

Overlay metrology solutions with both higher measurement accuracy/precision and process robustness are key factors when addressing increasingly tighter overlay budgets. Higher order overlay control and in-field metrology using smaller, micro-grating or other novel targets are becoming essential for successful production ramps and higher yields at 45 nm and beyond.

Examples of the widely adopted overlay measurement tools worldwide are KLA-Tencor's ARCHER [1], and the nanometrics [2] CALIPER series, overlay metrology platforms.