- MOS Technology 6522
The 6522 Versatile Interface Adapter (VIA) was an
integrated circuit made byMOS Technology , as well assecond source s includingRockwell andSynertek . It served as aI/O port controller for the 6502 family of microprocessors, providing the parallel I/O capabilities of the PIA as well astimer s and ashift register for serial communications. The 6522 was very popular in computers of the1980s , particularly Commodore's machines, and was also a central part of the designs of theApple III ,BBC Microcomputer andApple Macintosh .Input/output ports
The VIA contains 20 I/O lines, which are organised into 2 8-bit bidirectional ports (or 16 general-purpose I/O lines) and 4 control lines (for
handshaking andinterrupt generation). The directions for all 16 general lines (PA0-7, PB0-7) can be programmed independently. The control lines can be programmed to generate an interrupt when activated (all four), latch the corresponding I/O port (CA1 and CB1), automatically generate handshaking signals for devices on the I/O ports, or output a plain High or Low signal.Timers
The VIA provides 2 16-bit timer/counters, which can be used in one-shot (
monostable ) mode, free-running (divider ) mode or "pulse counting" mode, where the timer will monitor the 7th bit (PA6 or PB6) on its respective I/O port, and count how many state transitions pass by. Each timer can generate an interrupt when it reaches zero, and can also outputsquare wave s on the 8th bit of its respective I/O port (pin PA7 or PB7).Shift register
The VIA's shift register is bidirectional, 8 bits wide, and can run from either a timer-generated clock (from timer 2), the CPU clock, or an external source on line CB1. The serial input/output is on line CB2, and CB1 can also be programmed to output a bit clock for external devices. The infamous serial shift register bug is fixed by the CMD G65SC22.
Bugs
Aside from the aforementioned shift register bug, there was a potential register corruption problem that usually only occurred in systems using the 6522 with a processor having a non-6502-like bus, such as a
Motorola 68000 . If the address lines changed while chip select was inactive but the phase 2 clock input was high (active), register contents could be changed despite chip select being inactive. This was fixed in some but not all of the CMOS versions.
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