GgNMOS

ggNMOS is an abbreviation for grounded-gate NMOS. A ggNMOS is an electrostatic discharge (ESD) protection device used within CMOS integrated circuits (IC). The importance of using of such devices within ICs can been seen in the statistics reported by [1] , [2] in which 35% of all IC field failures are claimed to be associated with ESD damage.

Principle of Operation

tructure

As the implies, a ggNMOS device consists of a relatively large (W/L) NMOS device in which the gate, source, and base are tied together to ground. The drain of the ggNMOS is connected to the I/O pad under protection. A parasitic "npn" bipolar junction transistor (BJT) is thus formed with the drain (n-type) acting as the collector, the base/source combination (n-type) as the emitter, and the substrate (p-type) as the base. As is explained below, a key element to the operation of the ggNMOS is the parasitic resistance present between the emitter and base terminals of the parasitic npn BJT. This resistance is a result of the finite conductivity of the p-type doped substrate.

Operation

When a positive ESD event appears upon the I/O pad (drain) the collector-base junction of the parasitic npn becomes reverse biased to the point of avalanche breakdown. At this point the positive current flowing from the base to ground induces a voltage potential across the parasitic resistor, causing a positive voltage to appear across the base-emitter junction. The positive V_BE forward biases this junction, triggering the parasistic npn bipolar transistor.

References

[1] R. Merri and E. Issaq, “ESD design methodology,” "Proc. EOS/ESD. Symp.", pp. 223-237, 1993.

[2] T. Green, "A review of EOS/ESD field failures in military equipment," "Proc. EOS/ESD Symposium", pp.7- 14, 1988.

[3] A. Z. H. Wang, "On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective", Kluwer Acsdemic Publishing, Norwell, MA, 2002.