Stack machine

In computer science, a stack machine is a model of computation in which the computer's memory takes the form of one or more stacks. The term also refers to an actual computer implementing or simulating the idealized stack machine.

In addition, a stack machine can also refer to a real or simulated machine with a "0-operand" instruction set.In such a machine, most instructions implicitly operate on values at the top of the stack and replace those values with the result.Typically such machines also have a "load" and a "store" instruction that reads and writes to arbitrary RAM locations.(Like all other instructions, the "load" and "store" instructions in a typical stack machine need no operands -- they always take the RAM address from the top of the stack).

The advantage of stack machines ("0-operand instruction set") over accumulator machines ("1-operand instruction set") and register machines ("2-operand instruction set" or a "3-operand instruction set") is that programs written for a "0-operand" instruction set generally have higher code density than equivalent programs written for other instruction sets.

Stacks in automata theory

In automata theory, a stack machine has a number of stacks. The input is the initial content of stack 1; all the other stacks start empty. Each state of a stack machine is either a "read state" or a "write state"; and each state specifies a stack number to read (pop) from, or write (push) onto. In addition, a write state specifies the symbol to write, and the next state to transition to. A read state specifies, for each symbol in the alphabet, what state it would transition to if that symbol were read; in addition, it also specifies what state to transition to if the stack were empty. A stack machine halts when it transitions into a special halting state.

A stack machine with 1 stack is a very weak model of computation. For example, it can be shown that no 1-stack stack machine can recognize the simple language 0ⁿ1ⁿ (a number of 0s followed by the same number of 1s), via pumping arguments. The computational power of 1-stack stack machines is strictly greater than that of finite automata, but strictly less than that of deterministic pushdown automata.

A stack machine with multiple stacks, on the other hand, is equivalent to a Turing machine. For example, a 2-stack machine can emulate a TM by using one stack for the tape portion to the left of the TM's current head position and the other stack for the portion to the right.

Practical stack machines

Machines with a stack-based instruction set can have one or more stacks. Some stack machines are two-stack machines, with the two stacks usually being a "data stack" and a "return stack", the former for operations on data and the latter for return addresses. Other machines use the same stack for both.

A machine using processor registers for operands can easily simulate a stack machine. Such a simulation is sometimes called a "virtual stack machine". The advantage of a (more or less) stack-based instruction set (in hardware) over a register-based architecture, is shorter instructions, since less operand addresses have to be specified. This is the same as better code density and smaller compiled programs.

Commercial implementations of stack machines generally include a small set of special purpose registers for addressing enclosing contexts, i.e. stack frames that are not the topmost stack frame (dynamic vs lexical scoping are two different ways of using and accessing enclosing contexts). Practical stack machines are thus not identical to the stack machines of automata theory but allows a stack based CPU to be entirely suitable for general purpose computing.

Examples of commercial use of a stack machine include
* instruction set architectures directly executed in hardware
** the Burroughs large systems architecture (since 1961)
** Unisys Clearpath/MCP systems (latest implementation of Burroughs large systems architecture as of 2006)
** Tandem Computers T/16.
** HP 3000 (Classic, not PA-RISC)
** the Atmel MARC4 microcontroller [http://atmel.com/products/MARC4/]
** Several "Forth chips" [http://www.colorforth.com/chips.html] such as the RTX2000, the RTX2010, the Sh-Boom, the F21 [http://www.ultratechnology.com/f21.html] and the PSC1000 [http://www.developer.com/java/other/article.php/610041]
** [http://www.jwdt.com/~paysan/4stack.html The 4stack processor by Bernd Paysan] has four stacks.
**The [http://www.ptsc.com/products/igniteIP_data%20sheet_20050506.pdf "Ignite"] stack machine designed by Charles H. Moore holds a leading [http://www.eembc.org/benchmark/consumer.asp?HTYPE=SIM "functional density" benchmark] .

* virtual machines interpreted in software
** the UCSD Pascal p-machine (which closely resembled Burroughs)
** the Java virtual machine instruction set
** the VES (Virtual Execution System) for the CIL (Common Intermediate Language) instruction set of the ECMA 335 (Microsoft .NET environment)
** the Forth programming language, in particular the Forth virtual machine
** Adobe's PostScript
** Parakeet programming language
** Sun Microsystems' SwapDrop programming language for Sun Ray smartcard identification

Note that the Burroughs architecture combines a stack machine with tagged memory (a few bits in every memory word to describe the data type of the operands). Tagged memory requires fewer opcodes, e.g., a single "add" instruction works for any combination of integer and floating point operands. Requiring fewer opcodes means that the entire instruction set can fit into smaller opcodes, reducing the total instruction width.

See also

*Register machine

External links

* [http://www.ece.cmu.edu/~koopman/stack_computers/ "Stack Computers: the new wave" book by Philip J. Koopman, Jr. 1989]
* [http://www.excamera.com/articles/20/mp3c.html Homebrew CPU in an FPGA] - homebrew stack machine using FPGA
* [http://www.holmea.demon.co.uk/Mk1/Architecture.htm Mark 1 FORTH Computer] - homebrew stack machine using discrete logical circuits
* [http://www.holmea.demon.co.uk/Mk2/Architecture.htm Mark 2 FORTH Computer] - homebrew stack machine using bitslice/PLD
* [http://citeseer.ist.psu.edu/cache/papers/cs/31239/http%3AzSzzSzwww.complang.tuwien.ac.atzSzantonzSzivme03zSzproceedingszSzdavis.pdf/davis02case.pdf The Case for Virtual Register Machines] , Brian Davis, Andrew Beatty, Kevin Casey, David Gregg and John Waldron