Tukwila (processor)

Tukwila is the code-name for a future generation of Intel's Itanium processor family following Itanium 2 and Montecito. It is expected to come to market in late 2008. [cite web| url=http://news.zdnet.co.uk/emergingtech/0,1000000183,39286049-1,00.htm?r=2 |title=The Big Interview: Pat Gelsinger|date=26 February 2007|publisher=ZDNet] [cite web| url=http://blogs.intel.com/technology/2007/06/i_get_asked_regularly_about.html| title=An update on Intel Itanium processors| author=Pat Gelsinger| date=June 15 2007] While its features have not been publicly disclosed in detail, it is said to utilize both multiple processor cores (multi-core) and SMT techniques. The engineers said to be working on this project are ones acquired from the DEC Alpha effort, the EV8 iteration of which was to be focused on SMT.

Tukwila was previously code-named Tanglewood. However the name coincides with the Tanglewood music festival, and Intel renamed the project in late 2003.

The chip will have 4 processor cores per die and 30MB of cache [cite web| url=http://www.bit-tech.net/hardware/2008/03/19/intel_talks_nehalem_larrabee_and_32nm/1| title=Intel talks about Nehalem, Larrabee & 32nm| author=bit-tech.net| date=March 19 2008] ; it may only be able to run at full rated clock with some cores deactivated. In this way it can be configured for highest multithreaded performance or highest single thread performance, while staying within its thermal limits.

The processor should also be the first to pack more than 2 billion transistors on a single chip. [cite web| url=http://news.bbc.co.uk/2/hi/technology/7223145.stm| title=Chips pass two billion milestone| author=BBC News| date=February 4 2008] [cite web|url=http://www.computerworld.com/action/article.do?command=viewArticleBasic&articleId=9060900&intsrc=hm_list |title=Intel squeezes 2 billion transistors onto new Itanium chip |accessdate=2008-02-05 |author=Sharon Gaudin |date=2008-02-04 |work=Computerworld]

Xeon compatibility

It has been publicly disclosed that Tukwila and its associated chipset would bring socket compatibility between Intel's Xeon and Itanium processors, by introducing a new interconnect called Intel QuickPath Interconnect (QuickPath, previously known as Common System Interface or CSI). This ultimate endeavor would help reduce product development costs for both Intel and its partners, by allowing for greater reuse of components and manufacturing processes. [cite web| url=http://www.pcworld.com/news/article/0,aid,123190,00.asp| title=Intel Changes CPU Road Map| date=October 25 2005| publisher="PC World"] Tukwila is reported to have four "full" QuickPath links and two "half" links. [cite web| url=http://www.realworldtech.com/page.cfm?NewsID=361&section=news&date=05-05-2006#361| title=Intel’s Tukwila Confirmed to be Quad Core| date=5 May 2006]

Whitefield, the first Xeon processor to feature QuickPath, suffered significant project delays and was cancelled. [cite web| url=http://www.theregister.co.uk/2005/12/12/intel_csi_low/| title=Intel's CSI to outperform AMD's Hypertransport| date=12 December 2005| publisher="The Register"] The first processor to use QuickPath, the Intel Core i7, will be released in October 2008.

uccessor

The successor is codenamed Poulson. It is slated for a Q4 2009 release and will have over 4 cores, most likely eight. [ [http://pc.watch.impress.co.jp/docs/2008/0602/kaigai02l.gifIntel Server and Workstation Roadmap] Image] [ [http://www.theregister.co.uk/2008/07/11/ibm_power7_ncsa/ IBM Power7 (8 core), 4.0GHz] ]

"See" Itanium future processors

References