Torrenza

Torrenza is an initiative announced by AMD to improve support for the integration of specialized co-processors in systems based on AMD Opteron microprocessors. Torrenza does not refer to a specific product or specific technology, though the primary focus is on the integration of coprocessor devices directly connected to the Opteron processors' HyperTransport links, and other co-processors connected via PCI Express. The initiative's stated goals include improving technical and technology support for third party developers of coprocessing devices, reducing the cost of implementing HyperTransport interfaces on these devices, and improving the performance of the integrated system.

The Torrenza label is applied to both accelerator projects that pre-date the announcement of the program (on June 1, 2006) as well as projects announced more recently. Intel has followed suit by opening up its front side bus to third party companies [ [http://www.theregister.co.uk/2007/04/17/intel_idf_serverstuff/ The Register report] ] , alongside a PCI Express extension project jointly co-developed with IBM codenamed "Geneseo".

Goals

AMD expects tightly-integrated coprocessor technology to be a proving ground for developing and assessing those computational technologies that may eventually migrate onto the processor die itself. By building a platform that can accept 3rd party co-processors, the industry can build advanced hardware solutions and provide an environment for development of the application software required to support advanced hardware technology. Torrenza therefore is a stepping stone to the advanced CPU designs of the future and also provides a platform for software development needed for those hardware designs.

Technology

HyperTransport-connected devices can be installed in HTX slots or in Opteron CPU sockets. HTX slots are placed to allow access to external cabling and so are the natural location for network devices, such as the Qlogic Infinipath network adapter. As an alternative installation location, AMD CPU sockets provide access to the motherboard DRAM channels and support a larger power budget with room for the corresponding heat sink. In some system configurations, the CPU sockets provide access to multiple Hypertransport links that support higher frequencies than single 16-bit (per direction) 800 MHz link supported by the HTX slot.

Examples of devices that can be installed in AMD Opteron CPU sockets include DRC and XtremeData FPGA (Field Programmable Gate Array) co-processor modules. These fit in Socket 940 dual-socket motherboards and are based on Xilinx Virtex-4 and Altera Stratix II devices respectively. They both use HyperTransport to directly connect the FPGA devices to the other CPU socket and both provide memory controllers to access the socket's DDR DIMM slots on the motherboard. Tatari XTX accelerator card for offloading antivirus search from processor is another example [ [http://www.tgdaily.com/content/view/31823/135/ TGDaily report] ] .

Related Projects

* Torrenza is closely (though not exclusively) identified with HyperTransport technology and the HyperTransport Consortium.
* AMD is a supporter and partner of the recently formed OpenFPGA Consortium.
* The technology elements of Torrenza are closely related to those of the Fusion project, which targets the integration of graphics processing units (or other coprocessing functions) and CPU cores onto one chip. As a programmatic distinction, Torrenza refers to "external" acceleration technology (including graphics processing units in PCIe slots), while Fusion refers to "integrated" acceleration technology.
* The IBM Roadrunner supercomputer will connect 16,000 Opteron cores to 16,000 Cell Broadband Engines in an effort to reach 1 Petaflop of processing power. This would make the system the fastest supercomputer in the world. However, it is not clear if this system configuration should be considered an example of a coprocessing architecture because the Opteron and Cell processors will be running independent operating systems and communicating using software-based message-passing protocols.
* It is rumoured that the future IBM POWER7 processors are socket compatible with Opteron processors [ [http://www.theinquirer.net/default.aspx?article=38470 The Inquirer report] ] .

Press

* On June 1, 2006, AMD made the initial public announcement of the Torrenza program. [http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~109409,00.html]
* On September 21, 2006, AMD announced expanded support for the program. [http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~112780,00.html] The list of companies includes Cray, Fujitsu Siemens Computers, IBM, Sun Microsystems, Dell, Tarari and HP.

References

External links

* [http://www.hypertransport.org/ HyperTransport Consortium Home Page]
* [http://pc.watch.impress.co.jp/docs/2006/0713/kaigai287.htm PCWatch: The era of co-processors, AMD's "Torrenza" initiative] ( [http://translate.google.com/translate?hl=en&sl=ja&u=http://pc.watch.impress.co.jp/docs/2006/0713/kaigai287.htm&sa=X&oi=translate&resnum=1&ct=result&prev=/search%3Fq%3Dhttp://pc.watch.impress.co.jp/docs/2006/0713/kaigai287.htm%26hl%3Den%26lr%3D Machine Translation using Google] )
* [http://www.dailytech.com/article.aspx?newsid=4258&ref=y DailyTech report on the official announcement of Torrenza]
* [http://www.instat.com/promos/07/dl/IN0703889WHT_DahenUd9.pdf In-Stat report] , retrieved June 19, 2007