Time Stamp Counter

Time Stamp Counter

The Time Stamp Counter is a 64-bit register present on all x86 processors since the Pentium. It counts the number of ticks since reset, and is only accessible through the RDTSC instruction. This instruction returns the TSC in EDX:EAX. Its opcode is 0F 31. [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, [http://developer.intel.com/design/processor/manuals/253667.pdf] , Pp. 251–252] RDTSC was not formally part of the x86 assembly language when the Pentium was released, and was recommended for use by expert users or System Programmers only (Intel reference required). Pentium competitors such as the Cyrix 6x86 did not always have a TSC and may consider RDTSC an illegal instruction. Use of this instruction in Linux distributions precludes Linux from booting where the CPU does not support RDTSC. Cyrix included a Time Stamp Counter in their MII CPU architecture as RDTSC was formally included in the X86 assembly language in Pentium II.

The time stamp counter has, until recently, been an excellent high-resolution, low-overhead way of getting CPU timing information. With the advent of multi-core/hyperthreaded CPUs, systems with multiple CPUs, and "hibernating" operating systems, the TSC cannot be relied on to provide accurate results. The issue has two components: rate of tick and whether all cores (processors) have identical values in their time-keeping registers. There is no promise that the timestamp counters of multiple CPUs on a single motherboard will be synchronized. In such cases, programmers can only get reliable results by locking their code to a single CPU. Even then, the CPU speed may change due to power-saving measures taken by the OS or BIOS, or the system may be hibernated and later resumed (resetting the time stamp counter). Reliance on the time stamp counter also reduces portability, as other processors may not have a similar feature. Recent Intel processors include a constant rate TSC (identified by the constant_tsc flag in Linux's /proc/cpuinfo). With these processors the TSC reads at the processor's maximum rate regardless of the actual CPU running rate. While this makes time keeping more consistent, it can skew benchmarks, where a certain amount of spin-up time is spent at a lower clock rate before the OS switches the processor to the higher rate. This has the effect of making things seem like they require more processor cycles than they normally would.

Under Windows platforms, Microsoft strongly discourages using the TSC for high-resolution timing for exactly these reasons, providing instead the Windows APIs QueryPerformanceCounter and QueryPerformanceFrequency. [Game Timing and Multicore Processors [http://msdn2.microsoft.com/en-us/library/bb173458.aspx] , Pp. 251–252]

Starting with the Pentium Pro, Intel processors have supported out-of-order execution, where instructions are not necessarily performed in the order they appear in the executable. This can cause RDTSC to be executed later than expected, producing a misleading cycle count. [Using the RDTSC Instruction for Performance Monitoring [http://cs.smu.ca/~jamuir/rdtscpm1.pdf] ] This problem can be solved by executing a serializing instruction, such as CPUID, to force every preceding instruction to complete before allowing the program to continue.

Implementation in Various Processors

Intel processor families increment the time-stamp counter differently: [Intel 64 and IA-32 Architectures Software Developer's Manual [http://www.intel.com/products/processor/manuals/] , Volume 3B, Chapter 18]

* For Pentium M processors (family [06H] , models [09H, 0DH] ); for Pentium 4 processors, Intel Xeon processors (family [0FH] , models [00H, 01H, or 02H] ); and for P6 family processors: the time-stamp counter increments with every internal processor clock cycle.The internal processor clock cycle is determined by the current core-clock to busclock ratio. Intel SpeedStep technology transitions may also impact the processor clock.

* For Pentium 4 processors, Intel Xeon processors (family [0FH] , models [03H and higher] ); for Intel Core Solo and Intel Core Duo processors (family [06H] , model [0EH] ); for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H] , model [0FH] ): the time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may differ from the maximum qualified frequency of the processor; see Section 18.17.5 for more detail

The specific processor configuration determines the behavior. Constant TSC behavior ensures that the duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if the processor core changes frequency. This is the architectural behavior moving forward.

AMD processors always increment the time-stamp counter every clock cycle. [AMD64 Architecture Programmer's Manual [http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_11467_11513,00.html] Volume 3] Thus, power management features can change the number increments per second, and the values can get out of sync between different cores or processors in the same system. For Windows, AMD provides a utility [AMD Dual-Core Optimizer [http://www.amd.com/us-en/Processors/TechnicalResources/0,,30_182_871_13118,00.html?redir=COGA01] ] to periodically synchronize the counters on multiple core CPUs.

ee also

* HPET (high precision event timer)


External links

* [http://www.fftw.org/cycle.h cycle.h] - C code to read the high-resolution timer on many CPUs and compilers.
* [http://www.intel.com/cd/ids/developer/asmo-na/eng/downloads/209859.htm?page=2 Using the Processor Clocks]
* [http://www.cs.wm.edu/~kearns/001lab.d/rdtsc.html Programming examples]
* [http://lkml.org/lkml/2005/11/4/173 AMD engineer on TSC drift in AMD processors]

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