Interrupt descriptor table

The Interrupt Descriptor Table (IDT) is a data structure used by the x86 architecture to implement an interrupt vector table. The IDT is used by the processor to determine the correct response to interrupts and exceptions.

The details in the description below apply specifically to the x86 architecture and the AMD64 architecture. Other architectures have similar data structures, but may behave differently.

Use of the IDT is triggered by three types of events: hardware interrupts, software interrupts, and processor exceptions, which together are referred to as "interrupts". The IDT consists of 256 interrupt vectors.

Real Mode

In the 8086 processor, the IDT resides at a fixed location in memory from address 0000h to 03ffh, and consists of 256 four-byte real mode pointers (256 * 4 = 1024 bytes of memory). In the 80286 and later, the size and locations of the IDT can be changed in the same way as it is done in protected mode, though it does not change the format of it. A real mode pointer is defined as a 16 bit segment address and a 16 bit offset into that segment. A segment address is expanded internally by the processor to 20 bits thus limiting real mode interrupt handlers to the first 1 megabyte of addressable memory. The first 32 vectors are reserved for the processor's internal exceptions, and hardware interrupts may be mapped to any of the vectors by way of a programmable interrupt controller.

A commonly used x86 Real Mode interrupt is 0x10, the VGA BIOS code to handle primitive screen drawing functions.

Protected Mode

In Protected Mode, the IDT is an array of 8-byte descriptors stored consecutively in memory and indexed by an interrupt vector. These descriptors may be either Interrupt Gates, Trap Gates or Task Gates. Interrupt and Trap Gates point to a memory location containing code to execute by specifying both a segment (present in either the GDT or LDT) and an offset within that segment. The only difference between these two is that an Interrupt Gate will disable further processor handling of hardware interrupts, making it especially suitable to service hardware interrupts, while a Trap will leave hardware interrupts enabled and is thus mainly used for handling software interrupts and exceptions. Finally, a Task Gate will cause the currently active Task-State Segment to be switched, using the hardware task switch mechanism to effectively hand over use of the processor to another program, thread or process. Unlike the GDT, the programmer is allowed to store a descriptor in the first entry of the IDT, i.e. for interrupt vector 0 (which happens to be the divide by 0 exception).

The protected mode IDT may reside anywhere in physical memory. The processor has a special register (IDTR) to store both the physical base address and the length in bytes of the IDT. When an interrupt occurs, the processor multiplies the interrupt vector by 8 and adds the result to the IDT base address. With help of the IDT length, the resulting memory address is then verified to be within the table; if it is too large, an exception is generated. If everything is okay, the 8-byte descriptor stored at the calculated memory location is loaded and actions are taken according to the descriptor's type and contents.

A fully populated IDT is 2 KB (KiB) (256 entries of 8 bytes each) in length. It is not necessary to use all of the possible entries: it is sufficient to populate the IDT up to the highest interrupt vector used, and set the IDT length portion of the IDTR accordingly. Because of the limited number of exceptions, hardware interrupts, and software interrupts necessary and typically assigned to low vectors, many operating systems may limit the IDT in this way.

Vectors 0-31 are reserved by Intel for processor generated exceptions (general protection fault, page fault, etc.). Though currently only vectors 0-18 are used by the processor, future processors may create incompatibilities for broken software which use these vectors for other purposes.

External links

* [http://www.intel.com/products/processor/manuals/index.htm Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide]
* [http://www.osdever.net/bkerndev/Docs/idt.htm Bran's Interrupt Descriptor Table]