Single Stuck Line

Single Stuck Line is a fault model used in digital circuits. It is used for post manufacturing testing, not design testing. The model assumes one line or node in the digital circuit is stuck at logic high or logic low. When a line is stuck it is called a fault.

Digital circuits can be divided into -
1) Gate level or combinational circuits which contain no storage (latches and/or flip flops) but only gates like NAND, OR, XOR, etc.
2) Sequential circuits which contain storage.

This fault model applies to gate level circuits, or a block of a sequential circuit which can be separated from the storage elements.Ideally a gate-level circuit would be completely tested by applying all possible inputs, and checking that they gave the right outputs. This is physically impossible for circuits of any size. An adder to add two 32-bit numbers require 2⁶⁴ = 1.8*10¹⁹ tests, taking 58 years at 1 ns/test.

The "stuck at" fault model assumes that only one input on one gate will be faulty at a time, assuming that if more are faulty, a test that can detect any single fault, should easily find multiple faults.
To use this fault model, each input pin on each gate in turn, is assumed to be grounded, and a "test vector" is developed to indicate the circuit is faulty. Here a test vector is a collection of bits to apply to the circuit's inputs, and a collection of bits expected at the circuit's output. If the gate pin under consideration is grounded, and this test vector applied to the circuit, at least one of the output bits will not agree with that in the test vector. After obtaining the test vectors for grounded pins, each pin in turn is connected to a logic one and another set of test vector is developed to find these faults.
Each of these faults is called a single "stuck-at-0" or a single "stuck-at-1" fault respectively.

This model worked well for transistor-transistor logic (TTL), which was the logic of choice during the '70s and '80s. So well that manufacturers advertised how well they tested their circuits by a number called stuck-at fault coverage, which was the percentage of all possible stuck-at faults that their testing process would find.It also works moderately well for CMOS, unfortunately not all CMOS faults can be modeled by a stuck at model. CMOS has what is called a "stuck-open" fault which cannot be reliably tested with one test vector, and requires two to be applied sequentially. The model doesn't include bridging faults between adjacent signal lines, occurring e.g. in bus connections and array structures, as well. Nevertheless the concept of single stuck-at faults is widely used, and with some additional tests, has allowed industry to ship an acceptable low number of bad circuits.

The testing based on this model is aided by several things:
1) A test developed for a single stuck at fault often finds a large number of other stuck at faults.
2) A series of tests for stuck at faults will often, purely by serendipity, find a large number of other faults, like the stuck-open faults. This is sometimes called "windfall" fault coverage.
30 Another type of testing called "IDDQ testing" measures the way the power supply current of a CMOS integrated circuit changes, when a small number of slowly changing test vectors are applied. Since CMOS draws a very low current when its inputs are static, any increase in that current indicates a potential problem.

From http://pico1.e.ft.fontys.nl/publicad.html the simple serial fault simulator Faultsim, that is part of the Publicad design kit intended for educational purposes, can be downloaded free of charge.