image/svg+xml
InstructionRegister
InstructionDecoder
ControlLogic
I
R
1
+
_
1
+
_
MUX
MUX
W
Z
W'
Z'
B
B'
C
C'
D
D'
E
E'
H
L
H'
L'
IX
IY
PC
SP
TEMP
ACU
A
A'
F
F'
+
BUFFERS
BUFFERS
BUFFERS
ALU
Internal Data Bus 8 Bit
Address Bus 16 Bit
Control Bus
Control Section
Z80 Architecture