SIR-2

The SIR-2 instrument is a redesigned, highly compact, monolithic grating, near infrared spectrometer chosen to be a payload on the Indian Chandrayaan satellite. It is an ESA project, and is built by Max Planck Institute for Solar System Research, Polish Academy of Science and University of Bergen.

Mission

The mission of the instrument is to map the lunar surface in the near infrared spectrum from 0.9 - 2.4 μm with anunprecedented resolution of 6 nm. The purpose of this is to obtain information on the mineralcomposition of the moon, which in turn will help getting insight into a number of questions:

* What is the cause of the global asymmetry of the moon, which on the far side has a thicker crust and lacks the Mare structures which are characteristic for the near side?
* What was the early thermal evolution of the moon?
* What is the vertical and lateral structure of the lunar crust and how did it develop?
* What is the composition and structure of the lunar mantle?
* Why is the moon different from other planets and how do planets work in terms of surface processes, heat transfer, and geologic evolution?
* Are the Apollo geophysical measurements representative of the moon, or are they only valid for the small regions around the Apollo landing sites?

Similar missions

The instrument is a redesigned version of SIR, which was flown on board the SMART-1 technology satellite. SIR performed the same mission, but had a problem with dark current induced noise due to varying temperatures caused by differences in heat flux from the light and dark side of the moon. SIR-2 will attempt to improve this, mainly by using a detector with an embedded thermoelectric cooler and a digital controller to keep the detector temperature stable. This will stabilize the dark current noise, making it simple to subtract it since it will have an almost constant level.

Electronics

The control unit of SIR-2 is based on a System-on-a-chip design, minimizing the size and power consumption of the unit. A central component is the radiation hardened Axcelerator FPGA, containing a SPARC compliant CPU, communications interface Intellectual property cores, and custom interfaces to the rest of the instrument.