Paul Douglas Tougaw

Paul Douglas ("Doug") Tougaw, born July 3, 1969, is the chair of and a professor in the Department of Electrical and Computer Engineering at Valparaiso University. He received his B.S. in Electrical Engineering from the Rose-Hulmann Institute of Technology and his M.S. and Ph.D. in Electrical Engineering from the University of Notre Dame in 1995 [ [http://www-ssl.valpo.edu/engineering/coe/electrical/faculty.php Department of Electrical & Computer Engineering : College of Engineering : Valparaiso University ] ] . In 2005, Tougaw earned an MBA from Valparaiso University's College of Business Administration [ [http://www.valpo.edu/cba/programs/alumniprofiles.php#dTougaw alumniprofiles ] ] . His main area of research interest is in the field of Quantum Cellular Automata (QCA). [Christopher Graunke, David Wheeler, Douglas Tougaw, and Jeffrey D. Will, “Implementation of a crossbar network using quantum-dot cellular automata,” IEEE Transactions on Nanotechnology, vol. 4, no. 4, Jul. 2005 p. 1 - 6] He was recently awarded the "Best Regional Paper" award at the 2007 Conference of the American Society of Engineering Educators. He was also runner-up for the USA National IEEE Young Engineer award.

Doug Tougaw's contribution to the field of has focused on the building of medium-scale integration components such as full-adders from basic QCA gates as well as fault-tolerance studies of QCA wires.

Presently, Doug Tougaw is the Richardson Professor [Engineering Professor Tapped for Alumni Teaching Award http://www.valpo.edu/valpomag/faculty/engineering.php] and chair of the department of electrical and computer engineering at Valparaiso University [ [http://www.valpo.edu/engineering/coe/electrical/faculty.php Department of Electrical & Computer Engineering : College of Engineering : Valparaiso University ] ] .

Recent work with Quantum cellular automata (QCA) devices

Recently, Dr. Tougaw has developed a Quantum-dot Cellular Automata (QCA) device having normal QCA cells laid out in a planar structure, having a set of input lines and a set of orthogonal output lines. The device has clocking regions that control the flow of binary signals through the device. The input columns are driven by a separate input signal, and all the cells of each column align to match their input signal. These input columns then serve as drivers for output rows that act as serial shift registers under the control of clock signals applied to sub-sections of the rows. In this way, a copy of the contents of each of the input signals propagates along each of the output rows to an output cell. The output cells of each output row may be assigned their own, latching clock signal. [PCT Application WO2006133117 (December, 24 2006)]

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