Planar process

The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed [patent|US|3025589|Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959] [patent|US|3064167|Hoerni, J. A.: "Semiconductor device" filed May 15, 1960] by Jean Hoerni, one of the Traitorous Eight, while working at Fairchild Semiconductor.

The key concept was to view a circuit in its two-dimensional projection (a plane), thus allowing the use of photographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allowed the use of a series of exposures on a substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors). Together with the use of metallization (to join together the integrated circuits), and the concept of p-n junction isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

The process involves the basic procedures of silicon dioxide (SiO₂) oxidation, SiO₂ etching and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO₂ layer, etching contact vias to the transistors, and depositing a covering metal layer over the oxide, thus connecting the transistors without manually wiring them together.

References

Other

* [http://nobelprize.org/nobel_prizes/physics/articles/lecuyer/planar.html The Planar Process]
* [http://www.computerhistory.org/semiconductor/timeline/1959-invention-of-the-planar-manufacturing-process-24.html Invention of the “Planar” Manufacturing Process]