- Reiner Hartenstein
Reiner Hartenstein (born
December 18 ,1934 inBerlin ) is a German computer scientist. He is a professor ofComputer Science (Informatik) at theUniversity of Kaiserslautern . He earned all his academic degrees, including his Ph. D. (Dr.-Ing.), from the EE department at theKarlsruhe Institute of Technology . This is where in the 1960s he worked on image processing and pattern recognition for ProfessorKarl Steinbuch , an early pioneer ofartificial neural networks .In the early 1970s, Hartenstein became associate professor of Computer Science at the
University of Karlsruhe where he worked oncomputer architecture andhardware description language s. In 1977, he joined the University of Kaiserslautern as a full professor of the Computer Science Department and director of the Xputer Lab Reconfigurable Computing laboratory, where he worked on design methodologies for VLSI systems,electronic design automation , and reconfigurable computing architectures and compilers. In 1981, he served as a visiting professor at theUniversity of California at Berkeley .Returning from Berkeley, he founded the German multi-university project for VLSI design E.I.S., a forerunner of the EUROCHIP infrastructure funded by the European Union - following the world-wide
Mead & Conway revolution for separating VLSI design from technology and establishing it at its own discipline.Reiner Hartenstein is the initiator of the trailblazing
hardware description language KARL and the VLSI CAD framework having been implemented around it. In this context, he has proposed to use term rewriting in a top-down-methodology to automatically generate VLSI designs including structured floorplan layout from mathematical formula as a specification source. (Later this proposal has been inplemented byMauricio Ayala-Rincon ).His work on hardware description languages and on reconfigurable computing as well as on
configware/software-co-compilation are regarded as pioneering achievements. He is considered to be the initiator of the methodology ofsuper systolic array s (a generalization ofsystolic array s, also forcoarse-grained reconfigurable architectures, as well as of the anti machine paradigm (xputer or Kress/Kung machine paradigm) for reconfigurable parallel computers which are not instruction-stream-driven: the counterpart of the von Neumann paradigm. Hartenstein is credited of coining the termsAnti machine ,Configware ,Domino notation ,Generic Address Generator (GAG), Reconfigurable Computing Paradox,Structured hardware design ,Structured VLSI design , andSuper systolic array . Credited of being the father ofReconfigurable Computing he is frequently invited to give keynote addresses.Hartenstein is founder of the international workshop series "PATMOS" on ’’Low Power Integrated Circuit Design’’ and of the international workshop series on "Reconfigurable Computing Education" He is co-founder of
EUROMICRO and of the international conference seriesFPL onFPGA s, reconfigurable computing, and its applications.Awards
*IEEE life fellow
*SDPS fellow
*FPL fellow
*IFIP silver corePublications
Reiner Hartenstein has published 14 books and more than 400 technical papers, for example:
* 1977: "Fundamentals of Structured Hardware Design. A Design Language Approach at Register Transfer Language"; North Holland / American Elsevier, Amsterdam / New York 1977
* 1990: A. Hirschbiel et al.: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; Proc. InfoJapan'90, Tokyo, Japan, 1990
* 1993 R. Hartenstein: KARL and ABL, in J. P. Mermet (ed.): Fundamentals and Standards in Hardware Description Languages; Kluwer Academic Publishers, 1993.
* 1998 J. Becker, K. Schmidt et al.: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. Hawaii Int'l. Conf. on System Sciences (HICSS'98), Big Island, Hawaii,1998
* 2002 M. Herz et al. (invited paper): Memory Organization for Data-Stream-based Reconfigurable Computing; Proc. IEEE ICECS 2002, Dubrovnik, Croatia, 2002Links
* [http://ai.eecs.umich.edu/people/conway/Impact/Mead-Conway%20references.html The Mead-Conway VLSI Chip Design Revolution]
* [http://de.wikipedia.org/wiki/E.I.S.-Projekt E.I.S.-Projekt (in German language)]
* [http://xputers.informatik.uni-kl.de/xputer/history.html The History of Xputers]
* [http://xputers.informatik.uni-kl.de/staff/hartenstein/lot/ICECS2002Herz.pdf Memory Organization for Data-Stream-based Reconfigurable Computing]
* [http://xputers.informatik.uni-kl.de/karl/karl_history_fbi.html The History of KARL and ABL]
* [http://xputers.informatik.uni-kl.de/faq-pages/fqa.html#anchor81257 Speed-ups by Computer to Xputer migration]
* [http://hartenstein.de Hartenstein's home page]
* [http://www.patmos-conf.org homepage of the PATMOS workshop series]
* [http://helios.informatik.uni-kl.de/RCeducation homepage of the workshop series on Reconfigurable Computing Education]
* [http://xputers.informatik.uni-kl.de/fpl/ the FPL conference series]
* [http://fpl.org homepage of FPL 2007]
* [http://euromicro.org homepage of EUROMICRO]
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