IBM AP-101

The IBM AP-101 is an avionics computer, used most notably in the U.S. Space Shuttle, but also in the B-52 and F-15, among others. When it was designed, it was a high-performance pipelined processor with core memory. Today, its specifications are exceeded by many microprocessors. It remains in service (particularly on the space shuttle) because it works and is flight-certified, whereas to certify a replacement would cost hundreds of thousands or millions of dollars.

The AP-101, being the top-of-the-line of the System/4 Pi range, shares its general architecture with the System/360 mainframes. It has 16 32-bit registers, and uses a microprogram to define an instruction set of 154 instructions. Originally only 16 bits were available for addressing memory; later this was extended with four bits from the program status word register, allowing a directly addressable memory range of 1M locations.

The original AP-101 was built using TTL integrated circuits. The main memory was originally core memory, but the AP-101S upgrade in the early 1990s used semiconductor memory.

A shuttle uses five AP-101s as "general-purpose computers" (GPCs). Four operate in sync, for redundancy, while the fifth is a backup running software written independently. The shuttle software is written in HAL/S, a special-purpose high-level language, whereas AP-101s used by the US Air Force are mostly programmed in JOVIAL.

References

*Norman, P. Glenn, IBM Corp. (1987). "The new AP101S General-Purpose Computer (GPC) for the Space Shuttle". IEEE Proceedings, Volume 75, pp.308–319, 01 March 1987.
*Vandling, Gilbert C. "Organization of a Microprogrammed Aerospace Computer". Computer Design, pp.65–72, February 1975.

External links

* [http://spaceflight.nasa.gov/shuttle/reference/shutref/orbiter/avionics/dps/gpc.html NASA description of shuttle GPCs]
* [http://www.hq.nasa.gov/office/pao/History/computers/Ch4-3.html NASA history of AP-101 development]