The IEEE Standard 1164 defines a package design unit that contains declarations that support a uniform representation of a logic value in a VHDL hardware description. The standardization effort was based on the donation of the Synopsys MVL-9 type declaration.
The primary data type std_ulogic (standard unresolved logic) consists of nine character literals in the following order:
'U' - uninitialized
'X' - strong drive, unknown logic value
'0' - strong drive, logic zero
'1' - strong drive, logic one
'Z' - high impedance
'W' - weak drive, unknown logic value
'L' - weak drive, logic zero
'H' - weak drive, logic one
'-' - don't care
This system promoted a useful set of logic values that typical CMOS logic design could utilize in the vast majority of modeling situations. The 'Z' literal makes Tri-state buffer logic easy. The 'H' and 'L' weak drives permit wire-and and wire-or logic. Additionally, the 'U' state is the default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary.
In VHDL, the hardware designer makes the declarations visible via the following library and use statements:
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