Low dropout regulator

A low dropout or LDO regulator is a DC linear voltage regulator which can operate with a very small input-output differential voltage. The main components are a power FET and a differential amplifier (error amplifier). One input of the differential amplifier monitors a percentage of the output, as determined by the resistor ratio of R1 and R2. The second input to the differential amplifier is from a stable voltage reference (bandgap reference). If the output voltage rises too high relative to the reference voltage, the drive to the power FET changes so as to maintain a constant output voltage.

Overview

The adjustable low dropout regulator debuted on April 12, 1977 in an Electronic Design article entitled "Break Loose from Fixed IC Regulators". The article was written by Robert Dobkin, an IC designer then working for National Semiconductor. Because of this, National Semiconductor claims the title of "LDO inventor" [ [http://ldo.national.com LDOs, Low Dropout Regulators, Linear Regulators, CMOS Linear Regulator ] ] . Dobkin later left National in 1981 to found Linear Technology where he is currently chief technology officer [ [http://electronicdesign.com/Articles/Index.cfm?ArticleID=16406 Electronic Design Welcome ] ] .

Regulation

A regulator's dropout voltage determines the lowest usable supply voltage. If, for example, the LDO has a dropout voltage around 700mV (0.7V), a 3.3V output would require the input to be at least 4V. Thus the LDO may be specified to provide a fixed 3.3V output with a 4V to 5.5V input. The dropout voltage is related to the output current via the pass device on resistance. LDO differ from standard regulators in the type of pass device employed. A standard regulator may use a NMOS transistor output which is very easy to control, whereas a LDO will use a PMOS output which is harder to control due to its large output impedance. However, the PMOS transistor will not require its gate voltage to be driven high (threshold voltage). Thus the dropout voltage is only limited by the PMOS transistor on resistance. Alternative strategies include gate voltage pumping, which is often dismissed due to noise, power consumption and startup time constraints.

An LDO's output voltage variation is due primarily to a variation in the temperature of the constant voltage reference source and the differential amplifier characteristics, as well as the sampling resistor tolerance (R1 and R2).

Some LDOs employ a control or bias voltage that provides the ability to supply lower output voltages.

Quiescent Current

Among other important characteristics is the quiescent, or ground current (the current flowing through the system when no load is present), which creates a difference between the input and output currents. The series pass element, topologies, and ambient temperature are the primary contributors to quiescent current. Quiescent current and input/output limit the efficiency of LDO regulators and should thus be minimized.

External links

* [http://ldo.national.com/ National Semiconductor LDOs]

References