I²S

I²S, or Inter-IC Sound, or Integrated Interchip Sound, is an electrical serial bus interface standard used for connecting digital audio devices together. It is most commonly used to carry PCM information between the CD transport and the DAC in a CD player. The I²S bus separates clock and data signals, resulting in a very low jitter connection. Jitter can cause distortion in a digital-to-analog converter. The bus consists of at least three lines:

# Bit clock line
# Word clock line (also called word select line)
# And at least one multiplexed data line

You may also find the following lines:

# Master clock (typical 256 x bitclk)
# A multiplexed data line for upload

Normal I²S

I²S consists, as stated above, of a bit clock, a word select and the data line. The bit clock pulses once for each discrete bit of data on the data lines. The bit clock will operate at a frequency which is a multiple of the sample rate. The bit clock frequency multiplier depends on number of bits per channel, times the number of channels. So, for example, CD Audio with a sample frequency of 44.1kHz, with 32 bits of precision per (2) stereo channels will have a bit clock frequency of 2.8224MHz. The word select clock lets the device know whether channel 1 or channel 2 is currently being sent, since I²S allows two channels to be sent on the same data line. Transitions on the word select clock also serve as a start-of-word indicator. The Word clock line transitions once per Sample, so while the Bit clock runs at some multiple of the sample frequency, the word clock will always match the sample frequency. For a 2 channel (stereo) system, the word clock will be a square wave, with an equal number of Bit clock pulses clocking the data to each channel. In a Mono system, the word clock will pulse one bit clock length to signal the start of the next word, but will no longer be square, rather all Bit clocking transitions will occur with the word clock either high or low.

Standard I²S data is sent from MSB to LSB, starting at the left edge of the word select clock, with one bit clock delay. This allows both the Transmitting and Receiving devices to not care what the audio precision of the remote device is. If the Transmitter is sending 32 bits per channel to a device with only 24 bits of internal precision, the Receiver may simply ignore the extra bits of precision by not storing the bits past the 24th bit. Likewise, if the Transmitter is sending 16 bits per channel to a Receiving device with 24 bits of precision, the receiver will simply Zero-fill the missing bits. This feature makes it possible to mix and match components of varying precision without reconfiguration.

There are left justified I²S streams, where there is no bit clock delay and the data starts right on the edge of the word select clock, and there are also right justified I²S streams, where the data lines up with the right edge of the word select clock. These configurations however are not considered standard I²S.

I²S signals can easily be transferred via Ethernet-spec connection hardware (8P8C plugs and jacks, and Cat-5e and above cabling).

See also

* AC97
* I²C
* S/PDIF

External links

* [http://www.nxp.com/acrobat_download/various/I2SBUS.pdf Philips specification 1996]
* [http://www.anthemav.com/OldSitev1/pdf/i2Srev1.pdf A Low Jitter, Consumer/Professional Digital Audio Interface]