VLYNQ

VLYNQ is a proprietary interface developed by Texas Instruments and used for broadband products, such WLAN and modems, VOIP processors and audio and digital media processor chips. The chip implements a full-duplex serial communications interface that enables the extension of an internal bus segment to one or more external physical devices. The external devices are mapped into local, physical address space and appear as if they are on the internal bus. Multiple VLYNQ devices are daisy-chained, communication is peer-to-peer, host/peripheral. Data transferred over the VLYNQ interface is 8B/10B encoded and packetized.

Details

The VLYNQ bus signals include 1 clock signal [CLK] , and 1 to 8 Transmit lines [TX0 and TX1 …] , and 1 to 8 Receive lines [RX0 and RX1…..] . All VLYNQ signals are dedicated and driven by only one device. The transmit pins of one device connect to the receive lines of the next device. The VLYNQ bus will operate at a maximum clock speed of 125 MHz. However the actual clock speed is dependent on the physical device with the VLYNQ. So a device may have a clock speed other than 125 MHz. For example a device may have an internal 100 MHz [maximum] clock rate, or external 80 MHz [maximum] clock rate.

When clocked at 125 MHz, a single T/R pair then delivers an effective data throughput of about 73 Mbit/s (for single, 32-bit word transfers), while a dual T/R pair implementation delivers 146 Mbit/s, and a maximum eight-channel version delivers 584 Mbit/s. In-band flow-control lets the interface independently throttle the transmit and receive data streams.

If data packets contain four or 16 words, some of the overhead is eliminated. So on a single channel, data bursts of four words per packet can deliver an effective throughput of 133 Mbit/s. With 16 words per packet, the throughput goes up to 178 Mbit/s. With the maximum eight channels, an effective throughput of over 1400 Mbit/s can be achieved with 16 words per packet. Both the direction and clock source may be software configurable [may be device dependent] . Software may also be used to set the internal clock speed [may be device dependent] . Unused clock lines are held high via an internal pull-up. Unused RX or TX lines may require an external 47k pull-down resistor [may be device dependent] . Software selectable internal pull-downs for signals may be provided on some devices.

Packet format

The packet format is: SOP, 10 bits CMD1, 10 bits; or PktType, 10 bits CMD2, 10 bits; or AdMask, 10 bits ByteCnt, 10 bits Address, 10 bits [could be up to 4 words] Data, 10 bits [could be 'N' words long] EOP, 10 bits

8B/10B Encoding

:"main article: 8B/10B encoding"

The IBM patented encoding method used for encoding 8-bit data bytes to 10-bit Transmission Characters. Data bytes are converted to Transmission Characters to improve the physical signal such that the following benefits are achieved: bit synchronization is more easily achieved, design of receivers and transmitters is simplified, error detection is improved, and control characters (i.e., the Special Character) can be distinguished from data characters.

References

[http://www.ti.com/litv/pdf/sprue36a TMS320DM644x DMSoC VLYNQ Port User's Guide ] for VLYNQ as implemented on one recent media processor